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* Studienarbeit Christopher Odenbach *
* *
* WS98/99 *
* *
* mit Dank an Willi *
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* MOTOROLA MC68HC705X32 *
* *
* Initialising subroutine *
* *
* *
* *
* *
* *
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INIT EQU *
RSP ;reset stack pointer
JSR INIT_PROCESSOR
JSR INIT_PORTS
JSR INIT_CAN_IDENT
JSR INIT_MCAN_IF
JSR INIT_SCI_IF
JSR INIT_VARIABLES
JSR LOG_ONTO_MASTER
WAITLOOP wait
*WAITLOOP NOP ;use this line for the MMEVS instead
BRA WAITLOOP
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* Initializing Processor
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INIT_PROCESSOR EQU *
SEI
LDA MSC
ORA #$30 ;enable extern Interrrupts sensitive on neg. edge only
STA MSC
CLI
RTS
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* Initializing the PORTS
*
* Port B
* 7 6 5 4 3 2 1 0
* led2 led1 leba oeab irq6 r/w adr1 adr0
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INIT_PORTS EQU *
LDA #$F8 ;conf. Bit 3 as output to drive Khepera IRQ6
;Bits 4 and 5 as signals for external buffer
;and Bits 6 and 7 to drive LEDs
STA DDRB
LDA #$D0
STA PORT_B ;light LEDs, leba = 0, oeab = 1
CLRA
STA DDRC ;conf. Port C as input
LDA #$FF ;all bits on PORT A conf. as outputs
STA DDRA
CLRA
STA PORT_A ;output 0 to external buffer
BSET 5,PORT_B ;latch data on rising edge of leba
CLRX
STX DDRA ;configure PORT A as input
BCLR 4,PORT_B ;oeab = 0 => enable latch output to port A
; for reading
RTS
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* Initializing CAN identifiers
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INIT_CAN_IDENT EQU *
LDA PORT_C
AND #$1F ;take Bits 0-4
STA ID ;Khepera ID is set to external DIP-settings
; (ID = 000xxxxx)
LSLA ;shift 3 bits left
LSLA
LSLA
AND #$E0
STA SENDER_ID_1 ;left 3 bits of ID (SENDER_ID_1 = xxx00000)
LDA ID
AND #$03
LSLA ;shift 6 bits left
LSLA
LSLA
LSLA
LSLA
LSLA
STA SENDER_ID_2 ;right 2 bits of ID (SENDER_ID_2 = xx000000)
LDA #$00
STA MASTER ;Master ID = 000 00000
LDA #$00
STA SCI ;SCI identifier $00 = 000 00000
LDA #$20
STA K_BUS ;K_BUS identifier $20 = 001 00000
RTS
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* Initializing the MCAN interface
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INIT_MCAN_IF EQU *
LDA CSTAT
STA CSTAT_BUF
BRSET 3,CSTAT_BUF,CSTAT_LOOP
LDA #$02
STA CCOM
CSTAT_LOOP LDA CSTAT
STA CSTAT_BUF
BRSET 5,CSTAT_BUF,CSTAT_LOOP
LDA #$01 ;set RR Bit to access other registers
STA CCNTRL
LDA ID ;acceptance code = my own ID
STA CACC
LDA #$E0 ;Acceptance Mask = 11100000 -> compare the last five bits
STA CACM
LDA #$01 ;SJW=1xTscl, P=2 ==> Tscl = 2*P/f_osc = 1 īs @ 4MHz
STA CBT0
LDA #$B4 ;Tseg1=5, Tseg2=4, three samples per bit
STA CBT1 ;==> Tbit=10 īs => 100 KBit/s
LDA #$DF ;TX1 Push-pull, TX0 Push-pull inv., CAN mode 2
STA COCNTRL
LDA #$0A ;clear RR bit => MCAN will operate normally
STA CCNTRL
LDA #$84 ;RX0 passive, release receive buffer
STA CCOM ;CCOM is only writable when RR is clear
RTS
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* Initializing the SCI interface
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INIT_SCI_IF EQU *
LDA #$02
STA SCCR1
LDA #$2E ;receiver int., transm., receiver, rec. wake up enable
STA SCCR2
LDA #$C0
STA BAUD ;NP=13, NT=1, NR=1 => 9.6 KBaud @ 4 MHz, Fosc/2
RTS
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* Initializing variables
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INIT_VARIABLES EQU *
CLRA
STA BC_IN
LDX #$08 ;clear the RAM receive and transmit buffer
CLRA
NBTX STA RX_RAM-1,X
STA SCI_TX_RAM-1,X
DECX
BNE NBTX
LDA #01
STA RX_RAM_ACC ;set the receive RAM buffer access
CLRA
STA RX_CNT
STA RAM_READ
STA K_BUS_REQUEST
RTS
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* Log onto Master - Simply send the ascii character 'L' (login)
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LOG_ONTO_MASTER EQU *
LDA SENDER_ID_1
ORA MASTER
STA TBI ; store ID and Recipient
LDA SENDER_ID_2
ORA K_BUS
ORA #$01
STA TRTDL ; store ID and K/SCI Bit, Data length = 1
LDA #$4C ; Login command (= 'L')
STA TDS1
LDA #$81 ; set transmission request
STA CCOM
RTS
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